The present invention relates to a phase mixer and a delay locked loop including the same, and more particularly, to a phase mixer operating according to PVT variation and a delay locked loop including the same.
FIG. 1 is a circuit diagram of a conventional phase mixer 100.
Referring to FIG. 1, the phase mixer 100 includes first driving units 101 to 103 receiving a first input signal IN_1, and second driving units 104 to 106 receiving a second input signal IN_2. The phase mixer 100 mixes a phase of the first input signal IN_1 and a phase of the second input signal IN_2 to output a phase mixed signal MIX_OUT.
The phase mixer 100 mixes the phase of the first input signal IN_1 and the phase of the second input signal IN_2 by driving the first input signal IN_1 and the second input signal IN_2 with different driving strengths in response to phase control signals PH_CTRL<1:K>. The first and second driving units 101 to 106 may be implemented with inverters. The first and second driving units 101 to 106 are enabled or disabled in response to the phase control signals PH_CTRL<1:K>. As the number of the driving units enabled in response to the phase control signals PH_CTRL<1:K> increases, the first input signal IN_1 and the second input signal IN_2 are driven more strongly. The phase of the phase mixed signal MIX_OUT becomes close to the phase of one of the first and second input signals IN_1 and IN_2 which is driven more strongly. For example, if the first input signal IN_1 is driven more strongly than the second input signal IN_2, a phase difference between the phase mixed signal MIX_OUT and the first input signal IN_1 is smaller than that between the phase mixed signal MIX_OUT and the second input signal IN_2.
Meanwhile, since the first and second driving units 101 to 106 invert the first and second input signals IN_1 and IN_2, the phase mixed signal MIX_OUT need not be inputted to an inverter (not shown). Bubbles of the second driving units 104 to 106 receiving the phase control signals PH_CTRL<1:K> indicate the inversion.
The phase mixer 100 is used to eliminate skew between signals in a delay locked loop (DLL), a duty cycle corrector (DCC), a clock data recovery circuit, and so on. A delay locked loop including the phase mixer 100 of FIG. 1 will be described below with reference to FIG. 2.
FIG. 2 is a block diagram of a conventional delay locked loop including the phase mixer 100 of FIG. 1.
Referring to FIG. 2, the delay locked loop includes a phase comparator 201, a delay line 203, and a replica model 205.
The phase comparator 201 compares a phase of an external clock EXT_CLK with a phase of a feedback clock FB_CLK outputted from the replica model 205 and outputs a comparison signal CMP containing information on a phase difference between the external clock EXT_CLK and the feedback clock FB_CLK. The replica model 205 replicates or models process, voltage, and/or temperature (PVT) variations of clock delay components of a semiconductor device, and receives an internal clock CLK_OUT to output the feedback clock FB_CLK based on the PVT variations. For example, the replica model 205 may include components having same physical characteristics as the components of the semiconductor device and may receive the same external supply voltage and ground as the components of the semiconductor device. The delay line 203 outputs the internal clock CLK_OUT by delaying the external clock EXT_CLK in response to the comparison signal CMP in order to reduce the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK. The clock is locked when the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK cannot be further reduced.
The delay line 203 includes a plurality of delay units (not shown) and the phase mixer 100 of FIG. 1. The plurality of delay units delay the input signal by a unit delay value UNIT_DD through each delay unit. The delay unit 203 delays the external clock EXT_CLK by using the plurality of delay units to output a first coarse delay clock COARSE_CLK1 and a second coarse delay clock COARSE_CLK2. A phase difference corresponding to the unit delay value UNIT_DD exists between the first coarse delay clock COARSE_CLK1 and the second coarse delay clock COARSE_CLK2.
The phase mixer 100 mixes a phase of the first coarse delay clock COARSE_CLK1 and a phase of the second coarse delay clock COARSE_CLK2 to output the internal clock CLK_OUT whose phase is varied by a delay corresponding to one or more units of a unit phase value PH_VALUE. The unit phase value PH_Value of a clock may be a delay in phase (or in time) of a clock signal in relation to another clock signal such as a delay in phase of one of the first coarse delay clock COARSE_CLK1 and the second coarse delay clock COARSE_CLK2 to the other one. The unit phase value PH_VALUE is smaller than the unit delay value UNIT_DD, which is a delay of the external clock EXT_CLK through each delay unit of the delay line 203, and the phase mixer 100 can finely adjust the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK.
FIG. 3 is a timing diagram for explaining a delay operation of the delay line of FIG. 2.
Referring to FIG. 3, each of the delay units delays the external clock EXT_CLK to output the first coarse delay clock COARSE_CLK1 and the second coarse delay clock COARSE_CLK2 having the phase difference corresponding to the unit delay value UNIT_DD. The phase mixer 100 mixes the phase of the first coarse delay clock COARSE_CLK1 and the phase of the second coarse delay clock COARSE_CLK2 to output the internal clock CLK_OUT whose phase is finely varied by one or more of the unit phase value PH_VALUE.
Meanwhile, as described above, the phase of the internal clock CLK_OUT is finely varied according to the different driving strengths for the first coarse delay clock COARSE_CLK1 and the second coarse delay clock COARSE_CLK2. The driving strengths for the first coarse delay clock COARSE_CLK1 and the second coarse delay clock COARSE_CLK2 are changed according to the number of the driving units provided in the phase mixer 100. Thus, the unit phase value PH_VALUE for finely varying the phases of the first coarse delay clock COARSE_CLK1 and the second coarse delay clock COARSE_CLK2 is determined by the phase difference between the first coarse delay clock COARSE_CLK1 and the second coarse delay clock COARSE_CLK2, that is, a ratio of the unit delay value UNIT_DD to the number of the driving units provided in the phase mixer 100. For example, the unit phase value PH_VALUE is 1 if the unit delay value UNIT_DD is 3 and the number of the first driving units provided in the phase mixer 100 is 3 prior to process/voltage/temperature (PVT) variation. Units of the delay value and the phase value are omitted, and number representing the delay value and the phase value represents magnitude of the delay value and the phase value.
Meanwhile, if the PVT is varied, the unit delay value UNIT_DD may be changed. For example, when a driving voltage of the delay unit of the delay line 203 drops down, the unit delay value UNIT_DD of each delay unit increases. Therefore, as illustrated, the unit phase value PH_VALUE increases. For example, when the unit delay value UNIT_DD increases from 3 to 6, the unit phase value PH_VALUE increases to 2 because the number of the first and second driving units 101 to 106 is constant.
If the unit delay value UNIT_DD increases due to the PVT variation, the unit phase value PH_VALUE also increases. Thus, the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK is adjusted based on the increased unit phase value PH_VALUE. Consequently, after locking, the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK is also varied, that is, increased with the increase of the unit delay value UNIT_DD and the unit delay value PH_VALUE. The increase in the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK means increase of jitter.
Consequently, if the phase difference between the first input signal IN_1 and the second input signal IN_2 increases due to the PVT variation, the conventional phase mixer 100 outputs the phase mixed signal MIX_OUT whose phase is varied by the increased unit phase value PH_VALUE, leading to increase of jitter. The above problems may arise in the delay locked loop of FIG. 2 or duty cycle corrector employing the phase mixer 100.